1. Field of the Invention
The present invention relates to a multiprocessor system. More particularly, the present invention relates to an improvement of a multiprocessor system wherein a device or devices are commonly controlled by a plurality of processors.
2. Description of the Prior Art
A multiprocessor system is generally utilized in case where a plurality of processors commonly use a device or devices. Such devices comprise peripheral apparatuses for a computer such as a memory, a process input-output apparatus, a typewriter, a floppy disk and a cathode-ray tube display. In order to commonly control such devices, a multiprocessor system of a bus structure using a common bus is utilized as a cheap approach which is able to be fast processed.
FIG. 1 is a schematic block diagram of a prior art multiprocessor system. In FIG. 1, a plurality of processors 1l to 1n commonly control two devices 61 and 62, for example. To this end, local buses 2l to 2n of the respective processors 1l to 1n are connected to a bus selecting circuit 3. The bus selecting circuit 3 selects any of the local buses 2l to 2n and connects the same to a common bus 5. The devices 61 and 62 are commonly connected to the common bus 5. The bus selecting circuit 3 is controlled by a control signal from a bus controller 4. More particularly, if and when the bus controller 4 receives any one of the bus request signals REQl to REQn from the respective processors 1l to 1n, the bus controller 4 identifies the bus request signal to recognize which local bus of the local buses 2l to 2n should be connected to the common bus 5 so that a control signal is applied to the bus selecting circuit 3.
Accordingly, if and when the processor 1l, for example, outputs a bus request signal REQl, then the bus controller 4 controls the bus selecting circuit 3 so that the local bus 21 is connected to the common bus 5. As a result, the processor 1l can communicate with the devices 61 and 62.
On the other hand, in a stand-alone system having generally a single processor, an emergency processing request to the processor is sometimes generated from a device side. Such an emergency processing request comprises a generation of timing from an external signal for a processor input, and a generation of status changing signal for a device, such as a completion of job, fullness of the data or empty of the data. The stand-alone system is adapted such that an interrupt number is provided for each factor of requests from the device and a corresponding interrupt number is recognized when an interrupt signal is applied to the processor and the corresponding interrupt processing is performed. Since such interrupt is performed for each device, the number of necessary interrupt numbers are the number of devices which request an interrupt.
Even in a multiprocessor system as shown in FIG. 1, an interrupt request from the device side to the processor is generated in the same manner as the stand-alone system and thus an interrupt control is required. However, since a multiprocessor system includes a plurality of processors and a plurality of devices, there are many combinations thereof. For this reason, an interrupt control in the multiprocessor system is very much more complicated as compared with the above described stand-alone system and thus, unless such a complicated process is achieved, an interrupt from the device to the corresponding processor can not be processed. More particularly, assuming that the number of devices which request an interrupt is m, it is necessary to decide which processor of the n processors the m interrupt requests are made to.
For the reason described in the foregoing, a prior art multiprocessor system adopted the following approach. More particularly, in order to achieve an interrupt request from the device, an interrupt status signal is outputted to the common bus 5 and all of the processors 1l to 1n usually scan the interrupt status signals in a cyclic manner by means of a program, so that a generation of interrupt request is recognized. An alternative approach is that a device or devices requesting an interrupt are not provided as a device that the respective processors 1l to 1n can commonly control, but are connected to a local bus of a processor to be interrupted and thus are used as a dedicated device for the processor so that the same interrupt control as that in the stand-alone system is made.
As described in the foregoing, in accordance with a prior art multiprocessor system, in case where an interrupt request from a device to any of the processors is performed, an interrupt response is lowered since a scan is made in accordance with each program of each processor so as to recognize an interrupt. In addition, if a device is occupied by a specific processor, all other processors can not control the device. Furthermore, if a device is occupied by any of processors, the number of devices to be occupied should be the number of processors which require the device and thus the system is very expensive, which is a significant disadvantage.